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1. general description the pca9539; pca9539r is a 24-pin cmos device that provides 16 bits of general purpose parallel input/output (gpio) expansion with interrupt and reset for i 2 c-bus/smbus applications and was develo ped to enhance the nxp semiconductors family of i 2 c-bus i/o expanders. i/o expanders provide a simple solution when additional i/o is needed for acpi power switches, sensors, push buttons, leds, fans, etc. the pca9539; pca9539r consists of two 8-bit configuration (input or output selection), input, output and polarity inversion (active h igh or active low operation) registers. the system master can enable the i/os as either inputs or outputs by writing to the i/o configuration bits. the data for each input or output is kept in the corresponding input or output register. the polarity of the read regist er can be inverted with the polarity inversion register. all registers can be read by the system master. the pca9539; pca9539r is identical to the pca9555 except for the removal of the internal i/o pull-up resistor which greatly reduces power consumption when the i/os are held low, replacement of a2 with reset and a different address range. the pca9539; pca9539r open-drain interrupt ou tput is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. the power-on reset sets the registers to their default values and initializes the device state machine. in the pca9539, the reset pin causes the same reset/default i/o input configuration to occur without de-powerin g the device, holding the registers and i 2 c-bus state machine in their default state until the reset input is once again high. this input requires a pull-up to v dd . in the pca9539r however, only the device state machine is initialized by the reset pin and the internal general-purpose registers remain unchanged. using the pca9539r reset pin will only reset the i 2 c-bus interface should it be stuck low to regain access to the i 2 c-bus. this allows the i/o pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the i 2 c-bus is being restored. two hardware pins (a0, a1) vary the fixed i 2 c-bus address and allow up to four devices to share the same i 2 c-bus/smbus. 2. features and benefits ? 16-bit i 2 c-bus gpio with interrupt and reset ? operating power supply voltage range of 2.3 v to 5.5 v (5.0 v ? 10 % for pca9539pw/q900 aec- q100 compliant devices) ? 5 v tolerant i/os pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset rev. 7 ? 15 april 2014 product data sheet
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 2 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset ? polarity inversion register ? active low interrupt output ? active low reset input ? low standby current ? noise filter on scl/sda inputs ? no glitch on power-up ? internal power-on reset ? 16 i/o pins which default to 16 inputs ? 0 hz to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? offered in three different package s: so24, tssop24, and hvqfn24 3. ordering information [1] pca9539pw/q900 is aec-q100 compliant. contact i2c.support@nxp.com for ppap. 3.1 ordering options table 1. ordering information type number topside marking package name description version pca9539bs 9539 hvqfn24 plastic thermal enh anced very thin quad flat package; no leads; 24 terminals; body 4 ? 4 ? 0.85 mm sot616-1 pca9539rbs 539r pca9539d pca9539d so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 pca9539pw pca9539pw tssop24 plast ic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 pca9539pw/q900 [1] pca9539pw PCA9539RPW pa9539rpw table 2. ordering options type number orderable part number package packing method minimum order quantity temperature pca9539bs pca9539bs,115 h vqfn24 reel 7? q1/t1 *standard mark smd [1] 1500 t amb = ? 40 ? c to +85 ?c pca9539bs,118 hvqfn24 reel 13? q1/t1 *standard mark smd [1] 6000 t amb = ? 40 ? c to +85 ?c pca9539bshp hvqfn24 reel 13? q2/t3 *standard mark smd [2] 6000 t amb = ? 40 ? c to +85 ?c pca9539rbs pca9539rbs,118 hvqfn24 reel 13? q1/t1 *standard mark smd [1] 6000 t amb = ? 40 ? c to +85 ?c
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 3 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset [1] pin 1 in quadrant 1; see figure 2 . [2] pin 1 in quadrant 2; see figure 3 . 3.1.1 pin 1 quadrant indication pca9539d pca9539d,112 so24 standard marking * ic?s tube - dsc bulk pack 1200 t amb = ? 40 ? c to +85 ?c pca9539d,118 so24 reel 13? q1/t1 *standard mark smd [1] 1000 t amb = ? 40 ? c to +85 ?c pca9539pw pca9539pw,112 tsso p24 standard marking * ic?s tube - dsc bulk pack 1575 t amb = ? 40 ? c to +85 ?c pca9539pw,118 tssop24 reel 13? q1/t1 *standard mark smd [1] 2500 t amb = ? 40 ? c to +85 ?c pca9539pw/q900 pca9539pw/q900,118 tssop24 reel 13? q1/t1 *standard mark smd [1] 2500 t amb = ? 40 ? c to +125 ?c PCA9539RPW PCA9539RPW,118 tssop24 reel 13? q1/t1 *standard mark smd [1] 2500 t amb = ? 40 ? c to +85 ?c table 2. ordering options ?continued type number orderable part number package packing method minimum order quantity temperature fig 1. carrier tape pin 1 quadrant designations fig 2. pin 1 in q1 fig 3. pin 1 in q2 aaa-010180 round sprocket holes q1 q2 q3 q4 quadrant designations q1 = upper left q2 = upper right q3 = lower left q4 = lower right way into the reel ddd slq ddd slq
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 4 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 4. block diagram remark: all i/os are set to inputs at reset. fig 4. block diagram of pca9539; pca9539r pca9539 pca9539r power-on reset 002aad722 i 2 c-bus/smbus control input filter scl sda v dd input/ output ports io0_0 v ss 8-bit write pulse read pulse io0_2 io0_1 io0_3 io0_4 io0_5 io0_6 io0_7 input/ output ports io1_0 8-bit write pulse read pulse io1_2 io1_1 io1_3 io1_4 io1_5 io1_6 io1_7 a1 a0 reset lp filter v dd int
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 5 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 5. pinning information 5.1 pinning fig 5. pin configuration for so24 fig 6. pin configuration for tssop24 fig 7. pin configuration for hvqfn24 pca9539d int v dd a1 sda reset scl io0_0 a0 io0_1 io1_7 io0_2 io1_6 io0_3 io1_5 io0_4 io1_4 io0_5 io1_3 io0_6 io1_2 io0_7 io1_1 v ss io1_0 002aad719 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 int v dd a1 sda reset scl io0_0 a0 io0_1 io1_7 io0_2 io1_6 io0_3 io1_5 io0_4 io1_4 io0_5 io1_3 io0_6 io1_2 io0_7 io1_1 v ss io1_0 pca9539pw pca9539pw/q900 PCA9539RPW 002aad720 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aad721 pca9539bs pca9539rbs transparent top view io1_3 io0_4 io0_5 io1_4 io0_3 io1_5 io0_2 io1_6 io0_1 io1_7 io0_0 a0 io0_6 io0_7 v ss io1_0 io1_1 io1_2 reset a1 int v dd sda scl terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 6 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 5.2 pin description [1] hvqfn24 package die supply ground is connected to both v ss pin and exposed center pad. v ss pin must be connected to supply ground for pr oper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. table 3. pin description symbol pin description so24, tssop24 hvqfn24 int 1 22 interrupt output (open-drain) a1 2 23 address input 1 reset 3 24 active low reset input . driving this pin low causes: ? pca9539 to reset its state machine and registers ? pca9539r to reset its state machine, but has no effect on its registers io0_0 4 1 port 0 input/output 0 io0_1 5 2 port 0 input/output 1 io0_2 6 3 port 0 input/output 2 io0_3 7 4 port 0 input/output 3 io0_4 8 5 port 0 input/output 4 io0_5 9 6 port 0 input/output 5 io0_6 10 7 port 0 input/output 6 io0_7 11 8 port 0 input/output 7 v ss 12 9 [1] supply ground io1_0 13 10 port 1 input/output 0 io1_1 14 11 port 1 input/output 1 io1_2 15 12 port 1 input/output 2 io1_3 16 13 port 1 input/output 3 io1_4 17 14 port 1 input/output 4 io1_5 18 15 port 1 input/output 5 io1_6 19 16 port 1 input/output 6 io1_7 20 17 port 1 input/output 7 a0 21 18 address input 0 scl 22 19 serial clock line input sda 23 20 serial data line open-drain input/output v dd 24 21 supply voltage
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 7 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6. functional description refer to figure 4 ? block diagram of pca9539; pca9539r ? . 6.1 device address 6.2 registers 6.2.1 command byte the command byte is the first byte to follow the address byte during a write transmission. it is used as a pointer to dete rmine which of the following re gisters will be written or read. fig 8. pca9539; pca9539r device address r/w 002aad724 1 1 1 0 1 a1 a0 programmable slave address fixed table 4. command byte command register 0 input port 0 1 input port 1 2 output port 0 3 output port 1 4 polarity inversion port 0 5 polarity inversion port 1 6 configuration port 0 7 configuration port 1
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 8 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.2.2 registers 0 and 1: input port registers this register is an input-only port. it reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by register 3. writes to this register have no effect. the default value ?x? is determined by the externally applied logic level. 6.2.3 registers 2 and 3: output port registers this register is an output-only port. it reflects the outgoing logic levels of the pins defined as outputs by registers 6 and 7. bit values in this register have no effect on pins defined as inputs. in turn, reads from th is register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. 6.2.4 registers 4 and 5: polarity inversion registers this register allows the user to invert the polar ity of the input port register data. if a bit in this register is set (written with ?1?), the input port data polarity is inverted. if a bit in this register is cleared (written with a ?0?), the input port data polarity is retained. table 5. input port 0 register bit 7 6 5 4 3 2 1 0 symbol i0.7 i0.6 i0.5 i0.4 i0.3 i0.2 i0.1 i0.0 default xxxxxxxx table 6. input port 1 register bit 7 6 5 4 3 2 1 0 symbol i1.7 i1.6 i1.5 i1.4 i1.3 i1.2 i1.1 i1.0 default xxxxxxxx table 7. output port 0 register bit 7 6 5 4 3 2 1 0 symbol o0.7 o0.6 o0.5 o0.4 o0.3 o0.2 o0.1 o0.0 default 11111111 table 8. output port 1 register bit 7 6 5 4 3 2 1 0 symbol o1.7 o1.6 o1.5 o1.4 o1.3 o1.2 o1.1 o1.0 default 11111111 table 9. polarity inversion port 0 register bit 7 6 5 4 3 2 1 0 symbol n0.7 n0.6 n0.5 n0.4 n0.3 n0.2 n0.1 n0.0 default 00000000 table 10. polarity inversion port 1 register bit 7 6 5 4 3 2 1 0 symbol n1.7 n1.6 n1.5 n1.4 n1.3 n1.2 n1.1 n1.0 default 00000000
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 9 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.2.5 registers 6 and 7: configuration registers this register configures the dire ctions of the i/o pins. if a bit in this register is set (written with ?1?), the corresponding port pin is enabl ed as an input with high-impedance output driver. if a bit in this register is cleared (wri tten with ?0?), the corresponding port pin is enabled as an output. at reset, the device's ports are inputs. 6.3 power-on reset when power is applied to v dd , an internal power-on reset holds the pca9539; pca9539r in a reset condition until v dd has reached v por . at that point, the reset condition is released and the pca9539; pc a9539r registers and smbus state machine will initialize to their default states. thereafter, v dd must be lowered below 0. 2 v to reset the device. for a power reset cycle, v dd must be lowered below 0.2 v and then restored to the operating voltage. 6.4 reset input a reset can be accomplis hed by holding the reset pin low for a minimum of t w(rst) . in the pca9539 the registers and smbus/i 2 c-bus state machine will be held in their default state until the reset input is once again high. this input typically requires a pull-up to v dd . in the pca9539r, only the device stat e machine is initia lized. the internal general-purpose registers remain unchanged. using the pca9539r hardware reset pin will only reset the i 2 c-bus interface should it be stuck low to regain access to the i 2 c-bus. this allows the i/o pins to retain thei r last configured state so that they can keep any lines in their previously defined stat e and not cause system errors while the i 2 c-bus is being restored. 6.5 i/o port when an i/o is configured as an input, fets q1 and q2 are off, creating a high-impedance input. the input voltage may be raised above v dd to a maximum of 5.5 v. if the i/o is configured as an output, then either q1 or q2 is on, depending on the state of the output port register. care should be exercised if an external voltage is applied to an i/o configured as an output because of the low-impedance path that exists between the pin and either v dd or v ss . table 11. configuration port 0 register bit 7 6 5 4 3 2 1 0 symbol c0.7 c0.6 c0.5 c0.4 c0.3 c0.2 c0.1 c0.0 default 11111111 table 12. configuration port 1 register bit 7 6 5 4 3 2 1 0 symbol c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 default 11111111
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 10 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.6 bus transactions 6.6.1 writing to the port registers data is transmitted to the pca9539; pca9539r by sending the device address and setting the least significant bit to a logic 0 (see figure 8 ? pca9539; pca9539r device address ? ). the command byte is sent after the address and determines which register will receive the data following the command byte. the eight registers within the pca9539; pc a9539r are configured to operate as four register pairs. the four pairs are input ports, output ports, polarity inversion ports, and configuration ports. after sendi ng data to one register, the ne xt data byte will be sent to the other register in the pair (see figure 10 and figure 11 ). for example, if the first byte is sent to output port 1 (registe r 3), then the next byte w ill be stored in output port 0 (register 2). there is no limitation on the number of data bytes sent in one write transmission. in this way, each 8-bit regist er may be updated independently of the other registers. at power-on reset, all registers return to default values. fig 9. simplified schematic of i/os v dd i/o pin output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data polarity inversion register data 002aad723 ff data from shift register ff ff ff q1 q2 v ss to int
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 11 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 10. write to output port registers 1101a1a00 a s1 start condition r/w acknowledge from slave 002aad725 a scl sda a write to port data out from port 0 p t v(q) 987654321 command byte data to port 0 data 0 slave address 0000010 0 stop condition 0.0 0.7 acknowledge from slave acknowledge from slave data to port 1 data 1 1.0 1.7 a data out from port 1 t v(q) data valid fig 11. write to configuration registers 1101a1a00 a s1 start condition r/w acknowledge from slave 002aad726 a scl sda a p 987654321 command byte data to register data 0 slave address 0000110 0 stop condition lsb msb acknowledge from slave acknowledge from slave data to register data 1 lsb msb a
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 12 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.6.2 reading the port registers in order to read data from the pca9539; pca9539r, the bus master must first send the pca9539; pca9539r address with the least significant bit set to a logic 0 (see figure 8 ? pca9539; pca9539r device address ? ). the command byte is sent after the address and determines which register will be accessed. afte r a restart, the devi ce address is sent again, but this time the least significant bit is set to a logic 1. data from the register defined by the command byte will then be sent by the pca9 539; pca9539r (see figure 12 , figure 13 and figure 14 ). data is clocked into the re gister on the falling edge of the acknowledge clock pulse. after the first byte is read, additional bytes may be read but the data will now reflect the informa tion in the other register in the pair. for example, if you read input port 1, then the next byte read would be input port 0. there is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. remark: transfer can be stopped at any time by a stop condition. fig 12. read from register a s start condition r/w acknowledge from slave 002aad727 a acknowledge from slave sda a p acknowledge from master data (first byte) slave address stop condition s (repeated) start condition (cont.) (cont.) 1101a1a01 a 1 r/w acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter na no acknowledge from master command byte 1101a1a0 1 0 data from lower or upper byte of register lsb msb data (last byte) data from upper or lower byte of register lsb msb
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 13 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset remark: transfer of data can be stopped at any moment by a stop condi tion. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previously been set to ?00? (read input port register). fig 13. read input port register, scenario 1 1101a1a01 a s1 start condition r/w acknowledge from slave 002aad728 a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int 6543210 7 6543210 7 6543210 7 6543210 7 int t v(int_n) t rst(int_n)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 14 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset remark: transfer of data can be stopped at any moment by a stop condi tion. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previously been set to ?00? (read input port register). fig 14. read input port register, scenario 2 1101a1a01 a s1 start condition r/w acknowledge from slave 002aad729 a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int t v(int_n) t rst(int_n) data 00 data 10 data 03 data 12 data 00 data 01 t h(d) t h(d) data 02 t su(d) data 03 t su(d) data 10 data 11 data 12
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 15 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.6.3 interrupt output the open-drain interrupt output is activated w hen one of the port pins changes state and the pin is configured as an input. the interr upt is deactivated when the input returns to its previous state or the input port register is read (see figure 13 ). a pin configured as an output cannot cause an interrup t. since each 8-bit port is read independently, the interrupt caused by port 0 will not be cleared by a read of port 1 or the other way around. remark: changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. 7. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 15 ). 7.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is hi gh is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 16 ). fig 15. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 16. definition of start and stop conditions mba608 sda scl p stop condition s start condition
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 16 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 7.2 system configuration a device generating a message is a ?transmitter ?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 17 ). 7.3 acknowledge the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. ea ch byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must gen erate an acknowledge af ter the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transm itter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cloc ked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 17. system configuration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 18. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 17 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 8. application design-in information device address configured as 1110 100x for this example. io0_0, io0_2, io0_3 configured as outputs. io0_1, io0_4, io0_5 conf igured as inputs. io0_6, io0_7 and (io1_0 to io1_7) configured as inputs. fig 19. typical application pca9539 io0_0 io0_1 scl sda v dd (5 v) master controller scl sda int io0_2 v dd a1 a0 v dd v ss int 10 k sub-system 1 (e.g., temp sensor) io0_3 int sub-system 2 (e.g., counter) reset controlled switch (e.g., cbt device) v dd a b enable sub-system 3 (e.g., alarm system) alarm io0_4 io0_5 io0_6 10 digit numeric keypad v ss 002aad730 10 k 10 k 2 k 100 k (3) io0_7 io1_0 io1_1 io1_2 io1_3 io1_4 io1_5 io1_6 io1_7 reset reset 10 k
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 18 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 8.1 minimizing i dd when the i/os are used to control leds when the i/os are used to control leds, they are normally connected to v dd through a resistor as shown in figure 19 . since the led acts as a diode, when the led is off the i/o v i is about 1.2 v less than v dd . the supply current, i dd , increases as v i becomes lower than v dd . designs needing to minimize current consumpt ion, such as battery power applications, should consider maintaining the i/o pins greater than or equal to v dd when the led is off. figure 20 shows a high value resistor in parallel with the led. figure 21 shows v dd less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v i at or above v dd and prevents additional supply current consumption when the led is off. 9. limiting values fig 20. high value resistor in parallel with the led fig 21. device supplied by a lower voltage 002aac189 led v dd ledn 100 k v dd 002aac190 led v dd ledn 3.3 v 5 v table 13. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.0 v v i/o voltage on an input/output pin v ss ? 0.5 6 v i o output current on an i/o pin - ? 50 ma i i input current - ? 20 ma i dd supply current - 160 ma i ss ground supply current - 200 ma p tot total power dissipation - 200 mw t stg storage temperature ? 65 +150 ?c t amb ambient temperature operating all devices except pca9539pw/q900 ? 40 +85 ?c pca9539pw/q900 ? 40 +125 ?c t j(max) maximum junction temperature - 125 ?c
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 19 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 10. static characteristics [1] v dd must be lowered to 0.2 v for at least 5 ? s in order to reset part. [2] each i/o must be externally limited to a maximum of 25 ma and each octal (io0_0 to io0_7 and io1_0 to io1_7) must be limited to a maximum current of 100 ma for a device total of 200 ma. table 14. static characteristics fo r all devices except pca9539pw/q900 v dd = 2.3 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 - 5.5 v i dd supply current operating mode; v dd =5.5v; no load; f scl = 100 khz; i/o = inputs - 135 200 ? a i stb standby current standby mode; v dd = 5.5 v; no load; v i =v ss ; f scl = 0 khz; i/o = inputs -0.251 ? a standby mode; v dd = 5.5 v; no load; v i =v dd ; f scl = 0 khz; i/o = inputs -0.251 ? a v por power-on reset voltage [1] no load; v i =v dd or v ss - 1.5 1.65 v input scl; input/output sda v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i ol low-level output current v ol =0.4v 3 - - ma i l leakage current v i =v dd =v ss ? 1- +1 ? a c i input capacitance v i =v ss -610pf i/os v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i ol low-level output current v dd = 2.3 v to 5.5 v; v ol =0.5v [2] 89- ma v dd = 2.3 v to 5.5 v; v ol =0.7v [2] 10 11 - ma v oh high-level output voltage i oh = ? 8ma; v dd =2.3v [3] 1.8 - - v i oh = ? 10 ma; v dd =2.3v [3] 1.7 - - v i oh = ? 8ma; v dd =3.0v [3] 2.6 - - v i oh = ? 10 ma; v dd =3.0v [3] 2.5 - - v i oh = ? 8ma; v dd =4.75v [3] 4.1 - - v i oh = ? 10 ma; v dd =4.75v [3] 4.0 - - v i lih high-level input leakage current v dd =5.5v; v i =v dd --1 ? a i lil low-level input leakage current v dd =5.5v; v i =v ss -- ? 1 ? a c i input capacitance - 3.7 5 pf c o output capacitance - 3.7 5 pf interrupt int i ol low-level output current v ol =0.4v 3 - - ma select inputs a0, a1 and reset v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1- +1 ? a
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 20 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset [3] the total current sourced by all i/os must be limited to 160 ma (80 ma for io0_0 through io0_7 and 80 ma for io1_0 through io1_ 7). [1] v dd must be lowered to 0.2 v for at least 5 ? s in order to reset part. [2] each i/o must be externally limited to a maximum of 25 ma and each octal (io0_0 to io0_7 and io1_0 to io1_7) must be limited to a maximum current of 100 ma for a device total of 200 ma. [3] the total current sourced by all i/os must be limited to 160 ma (80 ma for io0_0 through io0_7 and 80 ma for io1_0 through io1_ 7). table 15. static characteristics for pca9539pw/q900 v dd =5.0v ? 10 %; v ss =0v; t amb = ? 40 ? c to +125 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 4.5 - 5.5 v i dd supply current operating mode; v dd =5.5v; no load; f scl = 100 khz; i/o = inputs - 135 200 ? a i stb standby current standby mode; v dd = 5.5 v; no load; v i =v ss ; f scl = 0 khz; i/o = inputs -0.251 ? a standby mode; v dd = 5.5 v; no load; v i =v dd ; f scl = 0 khz; i/o = inputs -0.251 ? a v por power-on reset voltage [1] no load; v i =v dd or v ss - 1.5 1.65 v input scl; input/output sda v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i ol low-level output current v ol =0.4v 3 - - ma i l leakage current v i =v dd =v ss ? 1- +1 ? a c i input capacitance v i =v ss -610pf i/os v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i ol low-level output current v dd =4.5v; v ol =0.5v [2] 89- ma v dd =4.5v; v ol =0.7v [2] 10 11 - ma v oh high-level output voltage i oh = ? 8ma; v dd =4.5v [3] 4.1 - - v i oh = ? 10 ma; v dd =4.5v [3] 4.0 - - v i lih high-level input leakage current v dd =5.5v; v i =v dd --1 ? a i lil low-level input leakage current v dd =5.5v; v i =v ss -- ? 1 ? a c i input capacitance - 3.7 5 pf c o output capacitance - 3.7 5 pf interrupt int i ol low-level output current v ol =0.4v 3 - - ma select inputs a0, a1 and reset v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1- +1 ? a
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 21 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 11. dynamic characteristics [1] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [2] t vd;dat = minimum time for sda data out to be valid following scl low. [3] c b = total capacitance of one bus line in pf. [4] t v(q) measured from 0.7v dd on scl to 50 % i/o output. [5] resetting the device while actively communicating on the bus may cause glitches or errant stop conditions. [6] upon reset, the full delay will be the sum of t rst and the rc time constant of the sda bus. table 16. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - ? s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - ? s t su;sto set-up time for stop condition 4.0 - 0.6 - ? s t vd;ack data valid acknowledge time [1] 0.3 3.45 0.1 0.9 ? s t hd;dat data hold time 0 - 0 - ns t vd;dat data valid time [2] 300 - 50 - ns t su;dat data set-up time 250 - 100 - ns t low low period of the scl clock 4.7 - 1.3 - ? s t high high period of the scl clock 4.0 - 0.6 - ? s t f fall time of both sda and scl signals [3] -30020+0.1c b 300 ns t r rise time of both sda and scl signals [3] - 1000 20 + 0.1c b 300 ns t sp pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns port timing t v(q) data output valid time [4] - 200 - 200 ns t su(d) data input set-up time 150 - 150 - ns t h(d) data input hold time 1 - 1 - ? s interrupt timing t v(int_n) valid time on pin int -4 - 4 ? s t rst(int_n) reset time on pin int -4 - 4 ? s reset timing t w(rst) reset pulse width 4 - 4 - ns t rec(rst) reset recovery time 0 - 0 - ns t rst reset time [5] [6] 400 - 400 - ns
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 22 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 22. definition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd fig 23. definition of reset timing in pca9539 sda scl 002aad732 t rst 50 % 30 % 50 % 50 % 50 % t rec(rst) t w(rst) reset ion after reset, i/os reconfigured as inputs start t rst ack or read cycle fig 24. definition of reset timing in pca9539r sda scl 002aad733 t rst 50 % 30 % 50 % 50 % 50 % t rec(rst) t w(rst) reset ion after reset, i/os unchanged; device state machine reset start t rst ack or read cycle
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 23 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 25. expanded view of read input port register fig 26. expanded view of write to output port register rise and fall times refer to v il and v ih . fig 27. i 2 c-bus timing diagram scl 002aad734 21 0 ap 70 % 30 % sda input 50 % int t v(int_n) t rst(int_n) t h(q) t su(d) scl 002aad735 21 0 ap 70 % sda output 50 % t v(q) scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab285 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 1 (d1) bit 0 (d0) 1 / f scl t r t vd;dat acknowledge (a) stop condition (p) 0.3 v dd 0.7 v dd 0.3 v dd 0.7 v dd
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 24 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 12. test information r l = load resistor. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance of z o of the pulse generators. fig 28. test circuitry for switching times fig 29. load circuit table 17. test data test load switch c l r l t v(q) 50 pf 500 ? 2 ? v dd pulse generator v o c l 50 pf r l 500 002aab284 r t v i v dd dut v dd open gnd c l 50 pf 002aac226 r l 500 from output under test 2v dd open gnd s1 r l 500
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 25 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 13. package outline fig 30. package outline sot137-1 (so24) 81,7 $ pd[ $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp lqfkhv r r ',0(16,216lqfkglphqvlrqvduhghulyhgiurpwkhruljlqdoppgl phqvlrqv 1rwh 3odvwlfruphwdosurwuxvlrqvripplqfkpd[lpxp shuvlghduhqrwlqfoxghg 627 ; z 0 $ $ $ e s ' + ( / s 4 ghwdlo; ( = f / y 0 $ $ $ \ ( 06 slqlqgh[ h pp vfdoh 62sodvwlfvpdoorxwolqhsdfndjhohdgverg\zlgwkp p 627
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 26 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 31. package outline sot355-1 (tssop24) 81,7 $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp r r ',0(16,216ppduhwkhruljlqdoglphqvlrqv 1rwhv 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghduh qrwlqfoxghg 3odvwlflqwhuohdgsurwuxvlrqvripppd[lpxpshuvlghdu hqrwlqfoxghg 627 02 z 0 e s = h slqlqgh[ $ $ $ / s 4 ghwdlo; / $ + ( ( f y 0 $ ; $ ' \ pp vfdoh 76623sodvwlfwklqvkulqnvpdoorxwolqhsdfndjhohdgve rg\zlgwkpp 627 $ pd[
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 27 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 32. package outline sot616-1 (hvqfn24) $ ( k e 81,7 \ h 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp ' k \ h h f ',0(16,216ppduhwkhruljlqdoglphqvlrqv 627 02 / y z pp vfdoh 627 +94)1sodvwlfwkhupdohqkdqfhgyhu\wklqtxdgiodwsdfndjh qrohdgv whuplqdoverg\[[pp $ pd[ $ $ f ghwdlo; \ \ & h / ( k ' k h h e ; ' ( & % $ h whuplqdo lqgh[duhd whuplqdo lqgh[duhd $ & & % y 0 z 0 h h ( 1rwh 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghdu hqrwlqfoxghg '
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 28 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 14. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 15. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 15.3 wave soldering key characteristics in wave soldering are:
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 29 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 15.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 33 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 8 and 19 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 33 . table 18. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 19. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 30 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 33. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 31 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 16. soldering: pcb footprints fig 34. pcb footprint for sot137-1 (so24); reflow soldering ',0(16,216lqpp $\ %\ ' ' *\ +\ 3 & *[ vrwbiu +[ 627 vroghuodqg rffxslhgduhd )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri62sdfndjh $\ %\ *\ & +\ +[ *[ 3 *hqhulfirrwsulqwsdwwhuq 5hihuwrwkhsdfndjhrxwolqhgudzlqjirudfwxdood\rxw 3 ' '[ 3
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 32 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 35. pcb footprint for sot355-1 (tssop24); reflow soldering ',0(16,216lqpp $\ %\ ' ' *\ +\ 3 & *[ vrwbiu +[ 627 vroghuodqg rffxslhgduhd )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri76623sdfndjh $\ %\ *\ & +\ +[ *[ 3 *hqhulfirrwsulqwsdwwhuq 5hihuwrwkhsdfndjhrxwolqhgudzlqjirudfwxdood\rxw 3 ' '[ 3
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 33 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 36. pcb footprint for sot616-1 (hvqfn24); reflow soldering 627 )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri+94)1sdfndjh 'lphqvlrqvlqpp $[ $\ %[ %\ ' 6/[ 6/\ 63[wrw 63\wrw 63[ 63\ *[ *\ +[ +\ 3 & q63[ q63\ vrwbiu rffxslhgduhd $[ %[ 6/[ *[ *\ +\ +[ $\%\6/\ 3 ' 63[wrw 63\wrw q63[ q63\ 63[ 63\ vroghuodqgsoxvvroghusdvwh vroghuodqg vroghusdvwhghsrvlw & *hqhulfirrwsulqwsdwwhuq 5hihuwrwkhsdfndjhrxwolqhgudzlqjirudfwxdood\rxw ,vvxhgdwh
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 34 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 17. abbreviations 18. revision history table 20. abbreviations acronym description acpi advanced configuration and power interface cbt cross-bar technology cdm charged-device model cmos complementary metal-oxide semiconductor esd electrostatic discharge fet field-effect transistor ff flip-flop gpio general purpose input/output hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output led light emitting diode smbus system management bus table 21. revision history document id release date data sheet status change notice supersedes pca9539_pca9539r v.7 20140415 product data sheet - pca9539_pca9539r v.6 modifications: ? table 1 ? ordering information ? : added table note [1] and table note [2] ? table 2 ? ordering options ? : ? added ?orderable part number? pca953 9bshp which has pin 1 in quadrant 2 (versus the pca9539bs,118 which has pin 1 in quadrant 1) ? ?packing method? descriptions are expanded ? added section 3.1.1 ? pin 1 quadrant indication ? pca9539_pca9539r v.6 20130206 product data sheet - pca9539_pca9539r v.5 pca9539_pca9539r v.5 20080728 product data sheet - pca9539_pca9539r v.4 pca9539_pca9539r v.4 20080519 product data sheet - pca9539 v.3 pca9539 v.3 20060921 product data sheet - pca9539 v.2 pca9539 v.2 (9397 750 14048) 20040930 product data sheet - pca9539 v.1 pca9539 v.1 (9397 750 12898) 20040827 product data sheet - -
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 35 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca9539_pca9539r all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all r ights reserved. product data sheet rev. 7 ? 15 april 2014 36 of 37 nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca9539; pca9539r 16-bit i 2 c-bus and smbus low power i/o port with interrupt and reset ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 15 april 2014 document identifier: pca9539_pca9539r please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1.1 pin 1 quadrant indication . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . . 7 6.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2.1 command byte . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2.2 registers 0 and 1: input port registers . . . . . . . 8 6.2.3 registers 2 and 3: output port registers. . . . . . 8 6.2.4 registers 4 and 5: polari ty inversion registers . 8 6.2.5 registers 6 and 7: config uration registers . . . . 9 6.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.6 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 6.6.1 writing to the port registers. . . . . . . . . . . . . . . 10 6.6.2 reading the port registers . . . . . . . . . . . . . . . 12 6.6.3 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 15 7 characteristics of the i 2 c-bus . . . . . . . . . . . . 15 7.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1.1 start and stop conditions . . . . . . . . . . . . . 15 7.2 system configuration . . . . . . . . . . . . . . . . . . . 16 7.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 application design-in information . . . . . . . . . 17 8.1 minimizing i dd when the i/os are used to control leds . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 10 static characteristics. . . . . . . . . . . . . . . . . . . . 19 11 dynamic characteristics . . . . . . . . . . . . . . . . . 21 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 24 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 14 handling information. . . . . . . . . . . . . . . . . . . . 28 15 soldering of smd packages . . . . . . . . . . . . . . 28 15.1 introduction to soldering . . . . . . . . . . . . . . . . . 28 15.2 wave and reflow soldering . . . . . . . . . . . . . . . 28 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28 15.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 29 16 soldering: pcb footprints. . . . . . . . . . . . . . . . 31 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 34 19 legal information . . . . . . . . . . . . . . . . . . . . . . 35 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 35 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36 20 contact information . . . . . . . . . . . . . . . . . . . . 36 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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